Successive approximation register (SAR) analog to digital converters (ADCs) are common in data acquisition systems in low power applications. Recent SAR ADCs have provided a sampling frequency (that is, the number of samples per second) in the megahertz region with, for example, a 12-bit resolution.
SAR ADCs can be suitable for low power applications as certain examples do not need active amplifiers and circuitries for their operations, and ideally need only a comparator to do a cycle of comparisons and a DAC that can be passive, e.g. capacitive or resistive.
A general block diagram of an example SAR ADC is shown in FIG. 1. The ADC 100 comprises a comparator 102, a digital to analog converter (DAC) 104 and successive approximation register and controller 106. The register and controller 106 receives a clock signal from clock generator 108. An analog input signal VIN 110 is provided to the negative input of the comparator 102, and the positive input receives a signal from the output of the DAC 104, which converts the digital register value to an analog signal.
Initially, the register value is set to zero and the analog input signal is sampled into the capacitive DAC. Then the sampled analog input is compared with different references that are generated by the capacitive DAC controlled by the successive register. The most significant bit (MSB) of the register is set to 1, thus the register value is set to around 50% of the full range of the register. Based on the output of the comparator, the MSB is either maintained at 1 or set to 0. For example, if the comparator output is 1, indicating that the register value (converted to analog by the DAC 104) is higher than the input signal VIN, the MSB is set to 0. This process is repeated for the next most significant bit (e.g. MSB-1) and successively for each bit in the register until the least significant bit LSB. At this point, the register contains a digital value representing the input signal VIN.
One of the main challenges in obtaining a better resolution for a SAR DAC, for example more than 11-12 bit resolution, is mismatch between unit components the DAC, such as mismatch in the capacitors in the DAC. In an example ideal capacitive DAC, each bit of a digital value provided to the DAC is associated with a capacitance that is an integer multiple of a unit capacitance. For example, the LSB may be associated with a capacitance C, the next more significant bit (LSB+1) is associated with a capacitance 2C, the next (LSB+2) with a capacitance 4C, and so on, until the MSB which is associated with a capacitance 2nC, where n+1 is the number of bits of the DAC. This arrangement of capacitor sizes is referred to as binary weighting.
However, a DAC may have mismatch between the capacitors, such that the capacitance of a capacitor associated with one or more bits may deviate from the ideal value of an integer multiple of unit capacitance.
Conventional solutions to overcome the mismatch issue include measuring capacitances and trimming each capacitance using smaller capacitors, or digital calibration using a precise ramp input or other well-defined input such as a sine wave. However, each known solution adds considerably to production time and cost and may require each device incorporating a SAR ADC to be connected to equipment to undergo a calibration process.